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| ir3623mpbf www.irf.com high frequency 2-phase, single or dual output synchronous step down controller with ou tput tracking and sequencing description the ir3623 ic is a high performance synchronous buck pwm controller that can be configured for two independent outputs or as a current sharing single output. since the ic does not contain integrated mosfet drivers it is ideal for controlling ipowir tm integrated power stage modules such as the ip2005 series of products. ir3623 enables output tracking and sequencing of multiple rails in either ratiometric or simultaneous fashion. the ir3623 features 180 o out of phase operation which reduces the required input/output capacitance. the switching frequency is programmable from 200khz to 1200khz per phase by use of an external resistor or the switching frequency can be synchronized to an external clock signal. other key features offered by the ir3623 include; two independent programmable soft starts, two independent power good outputs, precision enable input and under voltage lockout. the current limit is provided by sensing the low side mosfet's on-resistance for optimum cost and performance. the output voltages are monitored through dedicated pins to protect against open circuit and to improve response time to an overvoltage event. features ? dual synchronous controller with 180 o out of phase operation ? configurable to 2-independent outputs or current share single output ? output voltage tracking ? power up /down sequencing ? current sharing using inductor?s dcr ? +/-1% accurate reference voltage ? programmable switching frequency up 1200khz ? programmable over current protection ? hiccup current limit using mosfet r ds(on) sensing ? latched overvoltage protection ? dual programmable soft-starts ? enable ? pre-bias start-up ? dual power good outputs ? on board regulator ? external frequency synchronization ? thermal protection ? 32-lead mlpq package applications ? embedded telecom systems ? distributed point of load power architectures ? computing peripheral voltage regulator ? graphics card ? general dc/dc converters fig. 1: power up /down sequencing data sheet no.pd94717 revf ordering information pkg package pin parts parts t&r desig description count per tube per reel oriantaion m ir3623mpbf 32 73 ------- m ir3623mtrpbf 32 -------- 3000 fig a simultaneous powerup vo1 vo2 simultaneous powerdown vo1 vo2 vo1 vo2 ratiometric powerup vo1 vo2 ratiometric powerdown
ir3623mpbf www.irf.com package information 2 ja = 36 o c/w jc = 1 o c/w *exposed pad on underside is connected to a copper pad through vias for 4-layer pcb board design absolute maximum ratings (voltages referenced to gnd) ? vcc supply voltage .................... ...........................? - 0.5v to 16v ? pwm1, pwm2 ????????.????.???.. -0.5v to 16v ? pgood ???. ?????????? ?????.. -0.5v to 16v ? gnd to sgnd ???????????????? +/- 0.3v ? storage temperature range .......... .......................... -65c to 150c ? operating junction temperat ure range .................. -40c to 125c ? esd classification ?????????????? jedec, jesd22-a114 caution: stresses above those listed in ?absolute maximum rating? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ?absolute maximum rating? conditions for extended periods may affect device reliability. o c s e t 2 13 fb1 comp1 ss1/sd1 p h _ e n 2 p wm 2 v c c v ou t 3 comp2 ss2/sd2/mode ocgnd ovp_output e n a b l e r t g n d s g n d 4 5 6 7 8 9 10 11 12 17 18 19 20 21 28 29 30 31 32 pad 14 15 16 seq sync v sen1 22 23 24 v sen2 fb2 1 2 3 v r e f v p 2 25 26 27 p wm 1 p h _ e n 1 o c s e t 1 pgood1 5 v _ s n s pgood2 track2 track1 v p 1 ir3623mpbf www.irf.com recommended operating conditions 3 parameter sym test condition min typ max units output voltage accuracy fb1, fb2 voltage v fb 0.8 v -1 +1 % accuracy -40 o c ir3623mpbf www.irf.com 5 pin# pin name description 1 pgood1 power good pin out put for channel 1, open collector. this pin needs to be externally pulled high 2 pgood2 power good pin out put for channel 2, open collector. this pin needs to be externally pulled high 3 track2 sets the type of power up / down sequencing (ratiometric or simultaneously). if it is not used connect this pin to vout3. 4 v sen2 sense pin for ovp2 and power good 2, channel 2. if it is not used connect this pin to gnd. 5 ovp-output ovp output, goes high when ovp condition occurs 6 fb2 inverting inputs to the error amplifier2. if it is not used connect this pin to gnd 7 comp2 compensation pin for the error amplifier2 8 ss2/sd2/mode soft start for channel 2, can be used as sd pin. float this pin for current share single output application. if it is not used connect this pin to gnd. 9 ocset2 current limit set point for channel2 10 ph_en2 phase enable pin for channel2 11 pwm2 pwm output for channel2 12 vcc supply voltage for the internal blocks of the ic 13 v out3 output of the internal regulator 14 pwm1 pwm output for channel1 15 ph_en1 phase enable pin for channel1 16 ocset1 current limit set point for channel 1 17 ss1/sd1 soft start for channel 1, can be used as sd pin 18 comp1 compensation pin for the error amplifier1 19 fb1 inverting input to the error amplifier1 20 ocgnd ground connection for ocset circuit 21 v sen1 sense pin for ovp1 and power good, channel 1 22 track1 sets the type of power up / down sequencing (ratiometric or simultaneously). if it is not used connect this pin to vout3. 23 sync external synchronization pin 24 seq enable pin for tracking and sequencing 25 v p1 non inverting input of error amplifier1 26 v p2 non inverting input of error amplifier2. if it is not used connect this pin to gnd. 27 v ref reference voltage 28 sgnd signal ground 29 gnd ic?s ground 30 rt connecting a resistor from this pin to ground sets the switching frequency 31 enable enable pin, recycling this pin will rest ov, ss and prebias latch 32 5v_sns sensing either external 5v or the vout3 ir3623mpbf www.irf.com block diagram fig. 2: simplified bloc k diagram of the ir3623 6 ss2 bias generator two phase oscillator 0.8v 3v ramp1 sync sgnd pwm2 ss1 / sd comp2 error amp2 pwm2 por v out3 25ua pwm1 fb1 comp1 error amp1 pwm1 ramp2 64ua max uvlo fb2 vcc rt ss2 / sd/mode v p2 v ref pgood / ovp ocset2 ovp1 ocset1 25ua 64ua hiccup control ss1 ss2 mode regulator mode control por mode 0.8v ss 2 mode 20ua 20ua por 0.8v ss1 3ua 3ua v p1 ovp2 ovp1 ovp2 0.3v ss1 q r s por 0.3v ss2 q r s por ph_en2 ph_en1 pgood1 enable track2 seq sequencing ss1 / sd 5v_sns v sen1 pgood2 v out3 fault ctrl oc1,2 ss1,2 t. s ctrl1 ctrl2 ctrl2 thermal shutdown oc1 oc2 5v_sns ctrl1 tri-state ctrl1 ctrl2 tri_state mode v out3 v out3 v out3 por ovp_output gnd vcc track1 5v_sns ocgnd ocgnd v sen2 ir3623mpbf www.irf.com 7 7 typical operating characteristics vfb1 vs temperature 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 -40 -15 10 35 60 85 110 temperature (c) vfb1 (v) vfb2 vs tem perature 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 -40 -15 10 35 60 85 110 temperature (c) vfb2 (v) ss1 current vs tem perature -23.0 -22.0 -21.0 -20.0 -19.0 -18.0 -17.0 -16.0 -15.0 -40 -15 10 35 60 85 110 temperature (c) ss1 current (ua) vcc_uvlo vs tem perature 7.88 7.90 7.92 7.94 7.96 7.98 8.00 8.02 8.04 8.06 8.08 -40 -15 10 35 60 85 110 temperature (c) vcc_uvlo (v) vo3 vs tem perature 5.13 5.14 5.15 5.16 5.17 5.18 -40 -15 10 35 60 85 110 temperature (c) vo3 (v) ss2 current vs tem perature -23.0 -22.0 -21.0 -20.0 -19.0 -18.0 -17.0 -16.0 -15.0 -40 -15 10 35 60 85 110 temperature (c) ss2 current (ua) ir3623mpbf www.irf.com 8 8 typical operating characteristics max duty cycle vs temperature 600khz 75 76 77 78 79 80 -40 -15 10 35 60 85 110 temperature (c) max dut y c y cle ( % ) max duty cycle vs temperature 1.2mhz 54.0 55.0 56.0 57.0 58.0 -40 -15 10 35 60 85 110 temperature (c) max dut y c y cle ( % ) iocset1 vs tem perature 17.0 18.0 19.0 20.0 21.0 22.0 23.0 -40 -15 10 35 60 85 110 temperature (c) iocset1 (ua) iocset2 vs tem perature 17.0 18.0 19.0 20.0 21.0 22.0 23.0 -40 -15 10 35 60 85 110 temperature (c) iocset2 (ua) gm vs tem perature 3000 3100 3200 3300 3400 3500 3600 -40 -15 10 35 60 85 110 temperature (c) gm1 (umho) pwm freq 600khz vs tem perature 570 575 580 585 590 595 600 605 610 615 -40 -15 10 35 60 85 110 temperature (c) pwm1 freq (khz) ir3623mpbf www.irf.com circuit description 9 theory of opeartion introduction the ir3623 is a versatile device for high performance buck converters. it consists of two synchronous buck controllers which can be operated either in two independent outputs mode or in current share single output mode for high current applications. the timing of the ic is provided by an internal oscillator circuit which generates two-180 o -out-of- phase clock that can be externally programmed up to 1200khz per phase. the ir3623 when combined with ir?s ipowir power stage modules offers a compact and efficient solution where integration and power density are desired. under-voltage lockout the under-voltage lockout circuit monitors three signals (vcc, enable and 5v_sns). this ensures the correct operation of the converter during power up and power down sequence. the pwm outputs remain in the off state whenever one of these signals drop below set thresholds. normal operation resumes once these signals rise above the set values. figure 3 shows a typical start up sequence. 5v_sns ir3623 integrates an internal ldo for powering the external module without need for an external supply. for a correct start up sequence the external module needs to be biased first prior to the controller ic. the v out3 ramps up as soon as vcc is applied but the por (power on ready) is not enabled until the v out3 reached the 5v threshold set by 5v_sns pin. enable the enable features another level of flexibility for start up. the enable has precise threshold which is internally monitored by under-voltage lockout circuit. it?s threshold can be externally programmed to desired level by using two external resistors, so the converter doesn?t start up until the input voltage is sufficiently high. vcc 5.2v vout3 5v_sns enable vbus 4.7v 8.0v 11v 12v 12v ss 3v enable ok (ic's por) v out3 ok v cc ok seq fig. 3: normal start up, enable threshold is externally set to 11v ir3623mpbf www.irf.com 10 internal regulator ir3623 features an on-board regulator capable of sourcing current up to 200ma. this integrated regulator can be used to generate bias voltage an example of how this can be used to power the ip2005a is shown in figure 22. the output of regulator is protected for short circuit and thermal shutdown. out-of-phase operation the ir3623 drives its two output stages 180 o out- of-phase. in current share mode single output, the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same ripple voltage requirement. figure 4 shows two channels inductor current and the resulting voltage ripple at output. il1 il2 hdrv1 hdrv2 0dt t ic io mode selection the ir3623 can operate as a dual output independently regulated buck converter, or as a 2 phase single output buck converter (current share mode). the ss2 pin is used for mode selection. in current share mode this pin should be floating and in dual output mode a soft start capacitor must be connected from this pin to ground to program the start time for the second output. independent mode in this mode the ir3623 provides control to two independent output power supplies with either common or different input voltages. the output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. the error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, (pwm) which are applied to the external moseft drivers. figure 23 shows a typical schematic for such application. fig. 4: current ripple cancellation for output in addition, the 180 o out of phase contributes to input current cancellation. this result in much smaller input capacitor?s rms current and reduces the input capacitor quantity. figure 5 shows the equivalent rms current. single phase 2 phase duty cycle (vo/vin) rms current normalized (i rms /i out ) fig. 5: input rms value vs. duty cycle ir3623mpbf www.irf.com 11 current share mode this feature allows to connect both outputs together to increase curr ent handling capability of the converter to support a common load. in current sharing mode, error amplifier 1 becomes the master which regulates the common output voltage and the error amplifier 2 performs the current sharing function, figure 6 shows the configuration of error amplifiers. in this mode ir3623 make sure the master channel starts first followed by slave channel to prevent any glitch during start up. this is done by clamping the output of slave?s error amplifier until the master channel generates the first pwm signal. at no load condition the slave channel may be kept off depends on the offset of error amplifier. lossless inductor current sensing the ir3623 uses a lossless current sensing for current share purposes. the inductor current is sensed by connecting a series resistor and a capacitor network in parallel with inductor and measuring the voltage across the capacitor, this voltage is proportional to the inductor current. as shown in figure 6 the voltage across the inductor?s dcr can be expressed by: the voltage across the c 1 can expressed by: combining equations (1),(2) and (3) result to the following expression for v c1 : usually the resistor r 1 and c 1 are chosen so that the time constant of r 1 and c 1 equals the time constant of the inductor which is the inductance l 1 over the inductor?s dcr (r l1 ). if the two time constants match, the voltage across c 1 is proportional to the current through l 1 , and fig. 6: loss less inductor current sensing and current sharing l1 r l1 r1 l2 r l2 r2 c2 vp2 fb2 c1 v out master phase slave phase q2 q3 q4 + v c1 (s) - + v l1 (s) - v in v in il1 the sense circuit can be treated as if only a sense resistor with the value r l1 was used. the mismatch of the time constant does not affect the measurements of inductor dc current, but affects the ac component of the inductor current. soft-start the ir3623 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. it provides a separate soft-start function for each outputs. this will enable to sequence the outputs by controlling the rise time of each outputs through selection of different value soft-start capacitors. to ensure correct start-up, the soft-start sequence initiates when the vcc, enable and 5v_sns rise above their threshold and generate the power on reset (por) signal. soft-start function operates by sourcing an internal current to charge an external capacitor to about 3v. initially, the soft-start fu nction clamps the error amplifier?s output of the pwm converter. ) 1 ( - - - - sl r r v v s v 1 1 l 1 l out in 1 rl * * ) ( ) ( ? = ) 2 ( - - - - r i s v 1 l 1 l 1 rl * ) ( = ) 3 ( - - - - sc 1 r sc 1 v v s v 1 1 1 out in 1 c * * ) ( ) ( ? = ) 4 ( - - - - c sr 1 sl r i s v 1 1 1 1 l 1 l 1 c * * ) ( + + = 1 l 1 l c 1 l 1 1 1 r i s v r l c r if * ) ( * : = ir3623mpbf www.irf.com soft-start (cont.) during power up, the converter output starts at zero and thus the voltage at fb is about 0v. a current (64ua) injects into the fb pin and generates a voltage about 1.6v (64ux25k) across the negative input of error amplifier, see figure 7. the magnitude of this current is inversely proportional to the voltage at soft-start pin. the 28ua current source starts to charge up the external capacitor. in the mean time, the soft- start voltage ramps up, the current flowing into fb pin starts to decrease linearly and so does the voltage at negative input of error amplifier. when the soft-start capacitor is around 1v, the voltage at the negative input of the error amplifier is approximately 0.8v. as the soft-start capacitor voltage charges up, the current flowing into the fb pin keeps decreasing. the feedback voltage increases linearly as the injecting current goes down. the injecting current drops to zero when soft-start voltage is around 1.8v and the output voltage goes into steady state. figure 8 shows the theoretical operational waveforms during soft-start. the output start-up time is the time period when soft-start capacitor voltage increases from 1v to 2v. the start-up time will be dependent on the size of the external soft-start capacitor. the start- up time can be estimated by: for a given start up time, the soft-start capacitor (nf) can be estimated as: for normal start up the seq pin should be pulled high (usually can be connected to vout3). fig. 7: soft-start circuit for ir3623 fig. 8: theoretical operation waveforms during soft-start ) 5 ( - - - - v 8 0 ms t a 20 c start ss ) ( . ) ( * ) ( ? v 1 v 8 1 c t a 28 ss start ? = ? . 12 soft-start voltage voltage at negative input of error amp voltage at fb pin current flowing into fb pin 64ua 0ua 0v 0.8v ? 1.6v 0.8v 0v 3v ? 1.8v ? 1v output of por e/a2 vp2 fb2 ss2/sd2 i ss2 = 28ua track por ocp2 i hiccup2 = 3ua 64ua 3v e/a1 vp1 fb1 ss1/sd1 i ss1 = 28ua por ocp1 i hiccup1 = 3ua 64ua 3v seq ir3623mpbf www.irf.com 13 fig. 10: ratiometric power up /down output voltage tracking and sequencing the ir3623 can accommodate a full spectrum of user programmable tracking and sequencing options using track, seq, enable and power good pins. through these pins both simple voltage tracking such as that required by the ddr memory application or more sophisticated sequencing such ratiometric or simultaneously can be implemented. the seq pin controls the internal current sources to set the power up or down sequencing, toggle this pin high for power up and toggle this pin low for power down. the track pin is used to determine the second channel output for either ratiometric or simultaneously by using two external resistors. figure 9 shows how these pins are configured for different sequencing mode. e/a2 vp2 fb2 ss2/sd2 i ss2 = 28ua track2 por ocp2 i hiccup2 = 3ua 64ua 3v floating v o2 v o1 r c r d r e r f floating e/a1 vp1 fb1 ss1/sd1 i ss1 = 28ua por ocp1 i hiccup1 = 3ua 64ua 3v seq v ref v o1 r a r b c ss1 fig. 9: sequencing using track pin in general the r a and r b set the output voltage for the first output and r c and r d set the output voltage for the second output. for simultaneously vs. ratiometric, re and rf can be selected according to the table below: r b r d r f r a r c r e ratiometric simultaneously track pin fig. 11: simultaneously power up / down the track pin must be connected to vout3 if it is not used. for current share mode, high output voltage application (e.g. 5v) this pin needs to be connected to vcc. ir3623mpbf www.irf.com fault protection the ir3623 monitors the output voltage for over voltage protection and power good indication. it senses the r ds(on) of low side mosfet for over current protection. it also protects the output for prebias conditions. figure below shows the ic?s operating waveforms under different fault conditions. 14 ph_enable pwm ss tri_state pgood t 1 t 2 t 3 vo 1.0v 1.8v 90%vfb set voltage ocp threshold iout 3v por t 0 t 4 t 5 t 6 t 7 t 8 t 9 t 10 pre_bias voltage ov_output t 0 ?t 1 : vcc, 5v_sns and enable signals passed their respective uvlo threshold. ph_enable goes high and pwm switches high from tri-state. soft start sequence starts. t 1 ?t 2 : power good signal flags high. t 1 ?t 3 : output voltage ramps up and reaches the set voltage. t 4 ?t 5 : oc event, ss ramps down, ph-enable pulls low and pwm tri-states. ic in hiccup mode. t 5 ?t 6 : oc is removed, recovery sequence, fresh ss. t 6 ?t 7 : ph_enable goes high and pwm switches high from tri-state. output voltage reaches the set voltage. t 8 : ovp event. ph_enable is kept high and pwm is pulled low. ovp-output flags high to indicate ov event. t 9 ?t 10 : manually recycled the vcc after latched ovp. prebias start up. the ph_enable goes high after first internal pwm pulse is generated. the pwm output is kept in tri-state until ph-enable goes high. fig. 12: fault conditions ir3623mpbf www.irf.com over-current protection the over current protection is performed by sensing current through the r ds(on) of low side mosfet. this method enhances the converter?s efficiency and reduce cost by eliminating a current sense resistor. as shown in figure 13, an external resistor (r set ) is connected between ocset pin and the drain of low side mosfet (q2) which sets the current limit set point. the internal current source develops a voltage across r set . when the low side mosfet is turned on, the inductor current flows through the q2 and results a voltage which is given by: the ocp circuit starts sampling current 200ns (typical) after pwm signal goes high. the ocset pin is internally clamped to prevent false trigging, figure 15 shows the ocset pin during one switching cycle. fig. 13: connection of over current sensing resistor fig. 14: 3ua current source for discharging soft-start capacitor during hiccup an over current is detected if the ocset pin goes below ground. this trips the ocp comparator and cycles the soft start function in hiccup mode. the hiccup is performed by charging and discharging the soft-start capacitor in certain slope rate. as shown in figure 14 a 3ua current source is used to discharge the soft-start capacitor. the ocp comparator resets after every soft start cycles, the converter stays in this mode until the overload or short circuit is removed. the converter will automatically recover. during this fault condition the ph_en signal is low and pwm output is on tri-state, see figure 12. ss1 / sd 20 28ua 3ua ocp ) 6 ( - - - - ) i (r ) r (i v l ds(on) ocset ocset ocset ? ? ? = 0 ) i (r ) r (i v l ds(on) ocset ocset ocset = ? ? ? = ) 7 ( - - - - r i r i i on ds ocset ocset critical l set ) ( ) ( ? = = 15 fig. 15: ocset pin during normal condition ch1: inductor point, ch2:ldrv, ch3:ocset the value of r set should be checked in an actual circuit to ensure that the over current protection circuit activates as expected. the ir3623 current limit is designed primarily as disaster preventing, "no blow up" circuit, and doesn't operate as a precision current regulator. when the ss2 is floating over current on either phase would result to hiccup of output voltage. the critical inductor current can be calculated by setting: 22ua l1 r set ir3623 ocset i ocset v out hiccup control q1 q2 ip200x ocgnd i ocset * r ocset ir3623mpbf www.irf.com 16 ph_en and pre-bias for a correct start up the driver section needs to be powered up before the pwm signal is applied. ir3623 features a dedicated pin (ph_en) which can be used for this purposes. figure 22 shows how this pin is used to enable power stage modules. during normal start up the pwm is in tri-state mode until the ph_en goes high, each channel has it?s own ph_en pins. during the pre-bias start up the ph_en is kept low and the pwm output is in tri-state mode. the ph_en will be enabl ed as soon as the internal pwm signal is generated. over voltage protection over-voltage is sensed through two dedicated sense pins v sen1 , v sen2 . a separate ovp circuit is provided for each channel. the ovp threshold is user programmable and can be set by two external resistors. upon over- voltage condition of either one of the outputs, the ovp forces a latched shutdown on the fault output and pulls low the pwm signal. ir3623 features an ovp output signal, high status of this pin indicates the ovp event for either of the channels. this pin has 10ma current capability which can be used to drive an external switch. reset is performed by recycling the vcc or enable. power good the ir3623 provides two separate open collector power good signals which report the status of the outputs. the outputs are sensed through the two dedicated v sen1 and v sen2 pins. once the ir3623 is enabled and the outputs reach the set value (90% of set value) the power good signals go open and stay open as long as the outputs stay within the set values. these pins need to be externally pulled high. shutdown using soft start pins the outputs can be shutdown by pulling the soft- start pin below 0.3v. this can be easily done by using an external small signal transistor. during shutdown both mosfet drivers will be turned off. normal operation will resume by cycling soft start pin. switching frequency vs r t 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 0 25 50 75 100 125 150 175 200 225 r t (kohm) fsw(khz) fig. 16: switching frequency vs. external resistor (r t ) operating frequency selection the switching frequency is determined by connecting an external resistor (rt) to ground. figure 16 provides a graph of oscillator frequency versus rt. the maximum recommended channel frequency is 1.2mhz. frequency synchronization the ir3623 is capable of accepting an external digital synchronization signal. synchronization will be enabled by the rising edge at an external clock. per ?channel switching frequency is set by external resistor (rt). the free running frequency oscillator frequency is twice the per- channel frequency. during synchronization, rt is selected such that the free running frequency is 20% below the synchronization frequency. synchronization capability is provided for both single output current share mode and dual output configuration. when unused, the sync pin will remain floating and is noise immune. thermal shutdown temperature sensing is provided inside ir3623. the trip threshold is typically set to 135 o c. when trip threshold is exceeded, thermal shutdown turns off both mosfets. thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to normal range. there is a 20 o c hysteresis in the shutdown threshold. ir3623mpbf www.irf.com application information design example: the following example is a typical application for ir3623. the application circuit is shown in page24. output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb pin is the inverting input of the error amplifier, which is internally referenced to 0.8v. the divider is ratioed to provide 0.8v at the fb pin when the output is at its desired value. the output voltage is defined by using the following equation: when an external resistor divider is connected to the output as shown in figure 17. equation (8) can be rewritten as: for the calculated values of r 5 and r 6 see feedback compensation section. khz 600 f mv 30 v a 40 i v 8 1 v v 2 13 v 12 v s o o o in = = = = . max) , . ( , ) 8 ( - - - - r r 1 v v 5 6 ref o ? ? ? ? ? ? ? ? + ? = fig. 17: typical application of the ir3623 for programming the output voltage ) 9 ( - - - - v v v r r ref o ref 6 5 ? ? ? ? ? ? ? ? ? ? = soft-start programming the soft-start timing can be programmed by selecting the soft-start capacitance value. the start-up time of the converter can be calculated by using: where t start is the desired start-up time (ms) for a start-up time of 5ms, the soft-start capacitor will be 0.1uf. choose a ceramic capacitor at 0.1uf. input capacitor selection the 180 o out of phase will reduce the rms value of the ripple current seen by input capacitors. this reduces numbers of input capacitors. the input capacitors must be selected that can handle both the maximum ripple rms at highest ambient temperature as well as the maximum input voltage. the rms value of current ripple for duty cycle under 50% is expressed by: where: -i rms is the rms value of the input capacitor current -d 1 and d 2 are the duty cycle for each channel -i 1 and i 2 are the output current for each channel for io=40a and d=0.13, the i rms = 17.8a. ceramic capacitors are recommended due to their peak current capabilities, they also feature low esr and esl at higher frequency which enhance better efficiency, use 15x22uf, 16v ceramic capacitor from tdk (c3225x5r1c226m). for the single output application when the duty cycle is larger than 50% the following equation can be used to calculate the total rms value input capacitor current: ) 10 ( - - - - t a 20 c start ss * ? ( ) ( ) ( ) ) 11 ( - - - - d d i i 2 d 1 d i d 1 d i i 2 1 2 1 2 2 2 2 1 1 2 1 rms ? ? + ? = ( ) ( ) ( ) 0.5 d d 2 2 d 1 d 2 i i o rms > ? + ? = ir3623mpbf www.irf.com inductor selection the inductor is selected based on output power, operating frequency and efficiency requirements. low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor . the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: where: for 2-phase single output application the inductor ripple current is chosen between 10-40% of maximum phase current if , then the output inductor will be: l = 0.37uh the panasonic etqp4lr36wfc (l 1 =0.34uh, 24a, r l1 =1.1mohm) provides a low profile inductor suitable for this application. use the following equation to calculate c 12 and r 12 for current sensing: this results to c 12 =0.33uf and r 12 =1.1k s o in f 1 d t t i l v v ? = ? = ? ; ) ( i () ) 12 ( - - - - f i v v v v l s in o o in * ? ? ? = cycle duty d time on turn t frequency switching f current ripple inductor i voltage output v voltage input maximum v s o in = = = = = = output capacitor selection the voltage ripple and transient requirements determines the output capacitors types and values. the criteria is normally based on the value of the effective series resistance (esr). however the actual capacitance value and the equivalent series inductance (esl) are other contributing components, these components can be described as: since the output capacitor has major role in overall performance of converter and determine the result of transient response, selection of capacitor is critical. the ir3623 can perform well with all types of capacitors. as a rule the capacitor must have low enough esr to meet output ripple and load transient requirements, yet have high enough esr to satisfy stability requirements. the goal for this design is to meet the voltage ripple requirement in smallest possible capacitor size. therefore ceramic capacitor is selected due to low esr and small size. panasonic ecj2fb0j226m (22uf, 6.3v, x5r and eia 0805 case size) is a good choice. in the case of tantalum or low esr electrolytic capacitors, the esr dominates the output voltage ripple, equation (13) can be used to calculate the required esr for the specific voltage ripple. ) %( o i 35 i 18 current ripple inductor i ripple voltage output v f c 8 i v esl l v v -(13) - - - esr i v v v v v l o s o l c o in esl o l esr o c o esl o esr o o = = = ? ? ? ? ? ? = = + + = * * * * ) ( ) ( ) ( ) ( ) ( ) ( 1 l 1 12 12 r l c r = * ir3623mpbf www.irf.com feedback compensation the ir3623 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to provide a closed loop transfer function with the highes t 0db crossing frequency and adequate phase margin (greater than 45 o ). the output lc filter introduces a double pole, ? 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see figure 18). the resonant frequency of the lc filter expressed as follows: figure 16 shows gain and phase of the lc filter. since we already have 180 o phase shift just from the output filter, the system risks being unstable. the ir3623?s error amplifier is a differential-input transconductance amplifier. the output is available for dc gain control or ac phase compensation. the e/a can be compensated either in type ii or typeiii compensation. when it is used in typeii compensation the transconductance properties of the e/a become evident and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp pin to ground as shown in figure 19. this method requires that the output capacitor should have enough esr to satisfy stability requirements. in general the output capacitor?s esr generates a zero typically at 5khz to 50khz which is essential for an acceptable phase margin. the esr zero of the output capacitor expressed as follows: -(14 ) - - - c l 2 1 f o o lc ? ? = gain f lc 0db phase 0 f lc -180 frequency frequency -40db/decade fig. 18: gain and phase of lc filter the transfer function (ve/vo) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: the gain is determined by the voltage divider and e/a?s transconductance gain. first select the desired zero-crossover frequency (fo): use the following equation to calculate r 4 : where: v in = maximum input voltage v osc = oscillator ramp voltage f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter g m = error amplifier transconductance -(15 ) - - - c esr 2 1 f o esr * * ? = ve v out v ref r 5 r 6 r 4 c 9 e/a f z h(s) db frequency gain(db) fb comp c pole fig. 19: typeii compensation network and its asymptotic gain plot -(16 ) - - - sc c sr 1 r r r g s h 9 9 4 6 5 5 m + ? ? ? ? ? ? ? ? + = * * ) ( () [] -(18) - - - c r 2 1 f -(17 ) - - - r * r r r g s h 9 4 z 4 6 5 5 m * * * = ? ? ? ? ? ? ? ? + = 19 ( ) s o esr o f 1/10 ~ 1/5 f and f f * > -(19 ) - - - g r f v r r f f v r m 5 2 lc in 6 5 esr o osc 4 * * * ) ( * * * + = ir3623mpbf www.irf.com to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: using equations (18) and (20) to calculate c9. one more capacitor is sometimes added in parallel with c 9 and r 4 . this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: the pole sets to one half of switching frequency which results in the capacitor c pole : for a general solution fo r unconditionally stability for any type of output capacitors, in a wide range of esr values we should implement local feedback with a compensation network (typeiii). the typically used compensation network for voltage-mode controller is shown in figure 20. in such configuration, the transfer function is given by: the error amplifier gain is independent of the transconductance under the following condition: by replacing z in and z f according to figure 15, the transformer function can be expressed as: -(20) - - - c l 2 1 75 0 f f 75 f o o z lc z * * . % = = as known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the e/a output. it may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. the compensation network has three poles and two zeros and they are expressed as follows: cross over frequency is expressed as: c c c c r 2 1 f pole 9 pole 9 4 p + = * * * 2 f f for f r * 1 c 1 f r 1 c s p s 4 9 s 4 pole << ? ? = * * * v out v ref r 5 r 6 r 8 c 10 c 12 c 11 r 7 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain(db) h(s) db fb comp fig. 20: compensation network with local feedback and its asymptotic gain plot in m f m o e z g 1 z g 1 v v + ? = 20 ( ) [] ) ( * * * ) ( * ) ( ) ( 10 8 12 11 12 11 7 8 6 10 11 7 12 11 6 c sr 1 c c c c sr 1 r r sc 1 c sr 1 c c sr 1 s h + ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + = 6 10 8 6 10 2 z 11 7 1 z 12 7 12 11 12 11 7 3 p 10 8 2 p 1 p r c 2 1 r r c 2 1 f c r 2 1 f c r 2 1 c c c c r 2 1 f c r 2 1 f 0 f * * ) ( * * * * * * * * * * ? + = = ? ? ? ? ? ? ? ? ? + = = = o o osc in 10 7 o c l 2 1 v v c r f * * * * * = -(21) - - - 1 z * g and 1 z * g in m f m >> >> f r 2 1 c z 4 9 * * = ir3623mpbf www.irf.com based on the frequency of the zero generated by output capacitor and its esr versus crossover frequency, the compensation type can be different. the table below shows the compensation types and location of crossover frequency. the following design rules will give a crossover frequency approximately one-sixth of the switching frequency. the higher the band width, the potentially faster the load transient response. the dc gain will be large enough to provide high dc-regulation accuracy (typically -5db to -12db). the phase margin should be greater than 45 o for overall stability. desired phase margin: ceramic f lc ir3623mpbf www.irf.com layout consideration the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start to place the power components, make all the connection in the top layer with wide, copper filled areas. the inductor, output capacitor should be close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place input capacitors as close as possible to the power module?s input pin. add capacitors as necessary to reduce the esr to desired levels. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. in multilayer pcb use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. the exposed pad of ic should be connected to analog ground. layout guidelines for ip2005a can be found in the product data sheet. programming the current-limit the current-limit threshold can be set by connecting a resistor (r set ) from drain of low side mosfet to the ocset pin. the resistor can be calculated by using equation (7). the r ds(on) has a positive temperature coefficient and it should be considered for the worse case operation. this resistor must be placed close to the ic, place a small ceramic capacitor from this pin to ground for noise rejection purposes. = = = = ? = ? = ? = k r r a a i i m m r lim o set on ds 11 . 5 r current) output nominal over (50% 30 5 . 1 20 45 . 3 5 . 1 3 . 2 4 3 ocset ) ( ) ( 23 ) 7 ( - - - - r i r i i on ds ocset ocset critical l set ) ( ) ( ? = = ir3623mpbf www.irf.com fig. 22: application ci rcuit for single output 24 typical application ir3623mpbf www.irf.com 25 25 typical application fig. 23: application circuit for dual output ir3623mpbf www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed and qualified for the industrial market. visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 9/29/2008 (ir3623m) mlpq package; 5x5-32 lead 26 26 part marking pin 1 location logo part number date code (l = assem. location, y = year, ww = work week, p = pbf) 3623m lywwp feed direction figure a |
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